Low Power Mixed-Signal SoC Integration and Verification Challenges with Third Party IP Cores

New Challenges in Verification of Mixed-Signal IP and SoC Design

With the increasing demand in mobile and industry controller applications, a SoC design has more and more mixed-signal contents with the usage of some advanced power management techniques, such as power gating, dynamic voltage and frequency scaling etc. Traditional mixed-signal verification methodology relies on circuit simulation at different abstract levels. At the SoC level, mixed-signal fun...

Programmable Logic IP Cores in SoC Design: Opportunities and Challenges

As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed after fabrication. This paper outlines ways in which programmable logic cores can simplify SoC design,...

DVCon 2012: 131-II287: Low Power SoC Verification: IP Reuse and Hierarchical Composition using UPF

Power management is a critical feature of today’s SoCs, almost as important as functionality. IEEE 1801TM-2009 UPF enables specification of the intended power management infrastructure for an SoC to enable early verification and to drive implementation. Just as the complexity of an SoC demands a well-structured hierarchical approach to design and verification of its functional specification, th...

STREAMLINING ANALOG/MIXED-SIGNAL/RF VERIFICATION MEETING THE CHALLENGES OF SMALL RADIO FREQUENCY ICs DESIGN CHALLENGES FOR LOW-POWER, MIXED-SIGNAL CMOS SOCs AUTOMATING ANALOG IP PROCESS MIGRATION: THE NEXT FRONTIER SEMI-CUSTOM, VIA-CONFIGURABLE ANALOG AND MIXED-SIGNAL ASICs

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Mixed-signal SOC verification using analog behavioral models